expansion ROM burst support

[Gidi Bratman <gidi@galileo.co.il>]

Hi,

I have few questions regarding devices that implement expansion ROM:

1. During read from expansion ROM, is the device still restricted to the

16 cycles initial latency ? PCI-X spec explicitly mention that not, but
I
don't see similar statement in the conventional PCI spec

2. Must a device support burst access to expansion ROM ? Is a PCI-X
device allowed to NOT support read accesses to expansion ROM that
crosses 32-bit boundary, and terminate such accesses with target abort ?

3. Did you ever encounter PCI-X systems in which the host chip set
generate a burst read (read that crosses 32-bit boundary) to expansion
ROM ? Did you encounter conventional PCI systems that behave this way ?

Thanks,
--
Gidi Bratman
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