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Re: why chipset needn't PERR#?

Hi,

another reason may be that parity errors are not really expected to 
happen inside PCs.
I do agree that you're losing a bit of protection, but I've never seen a 
parity error happen on a PCI bus.

Ciao, Marco.

sushantsr@myw.ltindia.com wrote:
> ** Proprietary **
> 
> Hi Liu,
> 
> I dont know why the perticulat chepset dont have PERR# pin,
> but the chipset can detect polling, if there is any parity error found by the traget 
> See, in PCI header connfiguration, there is one bit in Status Register "Detected Parity Error"
> the chepset might be polling on fixed time to all devices to see whether any divice detected PERR??
> 
> OK, but this is not as effective as using PERR# and also it will affect the PCI bandwidth..
> have u got any other solution?
> 
> regards,
> ---sushant
> 
> 
>>>>" $(AÁõÔÆ·É" <liuyunfei@routerd.com> 11/22/02 08:07AM >>>
>>>
> Hi,experts
> We're using a chipset and I find that there is no PERR# pin within the PCI interface.And in the system the only PCI slot's PERR# pin is left unconnected(but with pull up resistor).
> I read in PCI spec that chipset used in mainboard is excluded from the requirement to implement the PERR# signal. According to the explanation of the PCI spec and Tom Shanley's "PCI system architecture",the chipset surely can learn whether parity error occurs when performing reading. But when initiating a write  ,how can the chipset get to know that a parity error is detected by the target? 
> The author of "PCI system architecture" explains this by assuming no PCI slots in system and no PERR# generated by PCI device. Obviously,it's just an assumption!Can anybody tell me how does a chipset get the information of detecting of parity errors by other devices?
> I'm confused about that and any light threw on me will be appreciated!
> Thanks in advance.
> 
> Liu Yunfei
> 
> 
> 
> 
> .
> 


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