Re: expansion ROM burst support

["Richard Iachetta" <iachetta@us.ibm.com>]

Gidi,

1) I didn't try to find a statement but I think a good assumption is that
the restriction does not exist.  The purpose of the restriction is not
functionality but latency fairness among multiple masters.  That
restriction plus others give masters a guaranteed worst case latency to
obtain ownership of the bus.  But expansion roms are only accessed at boot
time and at the time they are accessed, the only master is the host bridge.
No network masters worried about dropping frames are competing for the bus
at this time for example.

3) The host bridge doesn't really have any idea if it is accessing
expansion rom or some other memory.  The software running on the CPU would
know but the host bridge would not as far as I know.

2) A device does not have to support bursting to expansion rom space but
you cannot require the masters to restrict the kinds of transactions they
can issue.  Fortunately, the protocols give you a way to force the kinds of
transactions you want to see.  If you don't want to handle larger than
32-bit accesses, simply do not assert Ack64# when the transaction hits that
space and target disconnect the transaction after one beat (single data
phase disconnect in X-mode).  This will force all 32-bit transactions
regardless of what the master would have liked to have done.

Rich Iachetta
IBM Microelectronics Division -- Austin
System On a Chip / ASIC Development
Phone: 512-838-6305   Tie Line: 678-6305



                                                                                                                                          
                      Gidi Bratman                                                                                                        
                      <gidi@galileo.co.        To:       pci-sig@znyx.com                                                                 
                      il>                      cc:                                                                                        
                                               Subject:  expansion ROM burst support                                                      
                      12/11/02 08:11 AM                                                                                                   
                                                                                                                                          
                                                                                                                                          



Hi,

I have few questions regarding devices that implement expansion ROM:

1. During read from expansion ROM, is the device still restricted to the
16 cycles initial latency ? PCI-X spec explicitly mention that not, but I
don't see similar statement in the conventional PCI spec

2. Must a device support burst access to expansion ROM ? Is a PCI-X
device allowed to NOT support read accesses to expansion ROM that
crosses 32-bit boundary, and terminate such accesses with target abort ?

3. Did you ever encounter PCI-X systems in which the host chip set
generate a burst read (read that crosses 32-bit boundary) to expansion
ROM ? Did you encounter conventional PCI systems that behave this way ?

Thanks,
--
Gidi Bratman
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