Non-contiguous byte enables in memory space

[McDaniel Ryan-r55017 <r55017@motorola.com>]

I am wondering about the rationale behind supporting non-contiguous
byte enables in memory space. Do any devices or bus masters actually
do this in memory space? Are any actually capable of it?

The PCI 2.2 spec seems to leave a little wiggle room on supporting
this hardware in section 3.2.3:
"Since all PCI devices connect to the lower 32 bits for the address
decode, the device itself is required to provide this byte steering
when required, OR[my emphasis] the driver is required to place the
data on the correct byte."


It does not seem like it would be very wide spread.

Thanks,


Ryan