Re: Non-contiguous byte enables in memory space

["Peter Marek" <peter.marek@marekmicro.de>]

Hi,

yes, you will see non contiguos byte enables on PCI, although you will not
be able to define such data types in software.
So where does this come from ?

Consider these consecutive accesses
    - write 8bit to address 0x40000000
    - write 8bit to address 0x40000002

These two accesses fall within the same DWORD address. Because these are
write cycles, the may be buffered in posted write fifos in any bridge that
they have to cross (includes the host bridge and all PCi2PCI bridges). Most
bridges are intelligent enough to combine this two byte within one DWORD
accesses on the target side of the bus into a single access with non
contiguos byte enables on the other side. This is called merging and
combining and is only allowed for memory space, not for IO.

If you have problems with this (maybe because you need to have true 8bit
accesses and the order of accesses do matter), do the following
    - write 8bit to address 0x40000000
    - read a dummy address on the same board and neglect the data
    - write 8bit to address 0x40000002

This makes sure that you get two single writes on PCI. The read address must
be on the same board as the target of the writes to make sure this access
travels through the PCI hierarchy ( i.e. bridges) the same way that the
writes do.
Make sure that the compiler does not optimize the dummy read away, i.e.
declare the pointer as volatile.

Regards,


Peter Marek
General Director
MarekMicro GmbH
tel.: 049-9621-9732-110
fax: 049-9621-9732-199
www.marekmicro.de

----- Original Message -----
From: "McDaniel Ryan-r55017" <r55017@motorola.com>
To: <pci-sig@znyx.com>
Sent: Wednesday, December 11, 2002 8:42 PM
Subject: Non-contiguous byte enables in memory space


>
> I am wondering about the rationale behind supporting non-contiguous
> byte enables in memory space. Do any devices or bus masters actually
> do this in memory space? Are any actually capable of it?
>
> The PCI 2.2 spec seems to leave a little wiggle room on supporting
> this hardware in section 3.2.3:
> "Since all PCI devices connect to the lower 32 bits for the address
> decode, the device itself is required to provide this byte steering
> when required, OR[my emphasis] the driver is required to place the
> data on the correct byte."
>
>
> It does not seem like it would be very wide spread.
>
> Thanks,
>
>
> Ryan
>