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Master Wait States

To: PCI SIG Developers Forum <pci-sig@znyx.com>
Subject: Master Wait States
From: "Charles Neumann" <c.neumann@aristoslogic.com>
Date: Fri, 20 Dec 2002 13:56:50 -0800
Resent-Date: Fri, 20 Dec 2002 14:12:12 -0800
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Resent-Message-ID: <0KQGC.A.D_G.TT5A-@electra>
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Is anybody aware of PCI Masters that will actually insert waitstates at
the begining of a transaction, by delaying assertion of irdy?  I was
wondering if this is a reasonable corner case for testing?  Many thanks,

    - Charlie Neumann

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  - From: "Paul Miranda" <paul.miranda@amd.com>

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