Re: Master Wait States

[neal@dinigroup.com]

Back in the Virtex series of the Xilinx FPGAs (Not Virtex-E or Virtex-II), 
their 64/66 PCI core had to insert wait states until DEVSEL was asserted 
so that they knew the width of the bus (or something like that).


 On Fri, 20 Dec 2002, Charles Neumann wrote:

> Is anybody aware of PCI Masters that will actually insert waitstates at
> the begining of a transaction, by delaying assertion of irdy?  I was
> wondering if this is a reasonable corner case for testing?  Many thanks,
> 
>     - Charlie Neumann
> 

-- 
-- Neal Palmer

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