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Re: Master Wait States
Yes, I know that Socket 7 era SiS chipsets (http://www.sis.com.tw) do keep
IRDY# deasserted for a few cycles when starting a transaction before finally
asserting it.
I don't know about the recent ones (i.e., Pentium 4 or Athlon generation),
but it is likely that they still do that.
You can always check that by going to a computer dealer, buy one SiS
chipset-based motherboard, and hook up a logic analyzer to see how the PCI
bus behaves.
The PCI specification says that initiator has the right to insert wait
states when starting a transaction, as long as IRDY# is asserted within 8
clock cycles of the assertion of FRAME# (PCI 2.2 specification 3.5.2.
Master Data Latency).
Speaking of corner cases, you should also make sure that the PCI
interface you sound like you are working on can handle a burst configuration
transaction properly.
The specification says a burst configuration transaction is permitted, and I
heard that Intel 430FX chipset (Released in 1995) does actually perform it.
Always signal Disconnect with Data when responding to any configuration
transaction.
Kevin Brace
>From: "Charles Neumann" <c.neumann@aristoslogic.com>
>To: PCI SIG Developers Forum <pci-sig@znyx.com>
>Subject: Master Wait States
>Date: Fri, 20 Dec 2002 13:56:50 -0800
>
>Is anybody aware of PCI Masters that will actually insert waitstates at
>the begining of a transaction, by delaying assertion of irdy? I was
>wondering if this is a reasonable corner case for testing? Many thanks,
>
> - Charlie Neumann
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