RE: Single Data phase disconnection rules... PCI-X 2.0

[Tony Clark <Tony.Clark@EFI.COM>]

Varinder,

There is an implementation note on the next page titled "Single Data Phase
Disconnection and Memory Write Transactions" that explains the problem that
this situation can create for a PCI-X bridge. 

Tony Clark


> -----Original Message-----
> From: Varinder Sogi [mailto:varinder.sogi@dcmtech.co.in]
> Sent: Friday, January 10, 2003 6:04 AM
> To: PCISIG
> Subject: Single Data phase disconnection rules... PCI-X 2.0
> 
> 
> Hi Experts !!
> 
> 	In PCI-X 2.0 in the section "2.11.2.1 Single Data Phase 
> Disconnect (page 
> 149)", it says .....
> 
> "Target must be designed never to signal both Single Data 
> Phase Disconnect 
> and Data Transfer for memory write transactions that begin 
> four or less data 
> phases before any single ADB, unless the target verifies that 
> the byte count 
> is small enough not to include that ADB"
> 
> Could you please explain the reason behind this..
> 
> 
> Thanks and Regards,
> Varinder
>