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Minimum of 2 idle clks in PCI-X2.0
Can anyone let me know why there are mimimum of 2 idle clks(one idle clk
& other is the bus turn around clock) b/w transactions(from the same or
different initiators) in Mode 2 in PCI-X2.0. ?
Whereas in Mode 1 same initiator is permitted to start a new transaction
with a single idle clock b/w the 2 transactions.
Section 18.104.22.168 of PCI-X2.0 specs says "The second clock after the end
of the transaction is reserved for a bus turn around,whether there is
actual change of bus owernship or not."
In case of change of ownership b/w 2 transactions & bus turn around
alert getting signaled this makes sense whereas for same initiator a
single idle clk b/w transactions should be allowed .
i could not understand the reason behind it.
Pls explain me the same