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Configuration Transaction rule
Hi Experts,
Please see the following piece of text on page 60 of PCIX 1.0
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If the arbiter asserts GNT# to a device on clock N-2, the device starts
driving the bus for a configuration transaction (on clock N, N+1, or N+2),
and the arbiter deasserts GNT# before clock N+3, the device must not continue
the configuration transaction. It must float the bus two clocks after GNT# is
deasserted.
================================================================
In the above text it says, the arbiter deasserts GNT# before clock N+3.
Does it mean that the first GNT# high(deasserted) is sampled at N+3 clock, or
it means to say that it was deasserted even on the clocks before N+3 (i.e.
N+1 or N+2).
Because in both the cases the scenario is entirely different.
In the former case we can still continue the transaction, and in the later
one, we have to stop driving the bus.
Please clarify my doubt...
Thanks and Regards,
Varinder