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- RE: Burst Read in slave mode, (continued)
- driver for 21554,
richard.snijders
- Excess Retries to Bridge on Primary Side,
Pawitter Pal Singh
- RJ-45 jacks for PMC module ???,
Stuart Adams
- How ?,
Ingemi, John
- Technology 3GIO Bus,
OSWALDO HIDALGO
- JTAG pins,
Ted Firlit
- formula for adjusting pci clock?,
Tom Curran
- memory prefetchable,
Marco Serafini - QR s.r.l
- Need device to assert latencies on bus,
allan.boerner
- irdy on read,
Kevin Normoyle
- Arbitration/Ordering of Intel Chipset,
Hyun-Wook Jin
- pci interrupt acknowledge cycle,
BANESHWAR M SHANBHAG
- SSRAM question (off topic),
John W. Perry
- Re: Maximum Outstanding Split Transactions in PCI-X Configuration Controland Status Registers,
Richard Iachetta
- Maximum Outstanding Split Transactions in PCI-X Configuration Control and Status Registers,
Srividya Viswanathan
- Diodes to Vi/o? RE: PCI Signal clamping,
Lame Brooks-G14738
- PCI Signal clamping,
Mark van Nobelen
- Low Profile PCI,
Taylor, Mike
- INT Lines vs IRQs,
Chandrasekar Srinivasan
- Test Mail,
Chandrasekar Srinivasan
- Device Select Timing,
Siegfried Zeh
- PCI Compliance Certificate by PCISIG?,
Reichenbaecher, Olaf
- PMC clearances RE: Unidentified subject!,
Lame Brooks-G14738
- PCI Retry,
Ryan Mcdaniel
- IRQ and 21554.,
Christophe.LINDHEIMER
- 21154,
21cn
- Question about special cycle parity error,
Yanzhe Liu
- MASTER GNT# not being issued in response to REQ#,
Daniel DeConinck
- Master REQ# not receiving GNT#,
Daniel DeConinck
- burst length,
Marco Serafini - QR s.r.l
- July 27th PCI SIG membership meeting?,
Snyder, Cary D. (Cahners)
- looking for pci computers in VITA-32 PMC format,
Angel Guirao Elias
- PCI bus monitor/cycle generator,
James Murray
- PCI-Local-Bus-Switch Chip Manufacturer,
emmbeh
- How do I read the IRQ Routing Table with Assembler?,
Siegfried Zeh
- what is master retry timer?,
Sanjay Cartic
- PCI to PCI bridges,
Andrew Krenz
- Command Register IO and Mem Enable Bit,
Bert Marston
- How to access the pci configuration space?,
=?gb2312?B?zfXo6w==?=
- pci clock frequency,
Yao Zehui
- IO space devices,
Ryan Mcdaniel
- AD_OE timing,
Weng Tianxiang
- State of Arbiter GNT during PCI Reset,
James Murray
- Arbitration Code example,
James Murray
- FIFO in PCI memory space,
jula
- Using Multiple BAR's,
Bearzi, Anthony
- IDE bridge chips, address decoding and byte enables,
Ryan Mcdaniel
- RE: access PCI memory from DOS, or linux?,
Gord Wait
- access PCI memory from DOS,
JohanHZ
- RE: PCI2.2 Master Transaction Claiming,
Richard Walter
- VHDL Model For PLX ?,
Thomas Ebert
- pci master retry timeout value,
Sanjay Cartic
- pci trace impedance,
Hofmans, Kim
- max write completion time,
Sanjay Cartic
- RE: Maximum load of PCI-BUS,
Ingraham, Andrew
- WG: Maximum load of PCI-BUS,
Becker, Karsten
- 25MHz PCI Interface,
Weng Tianxiang
- Endian Mapping,
Amit Shah
- Re: pci tutorial,
burched - tony burch
- PCI-X Bus loading in Pf,
Brent Barr
- Unknown Vendor ID,
Alan Shu
- Null Data Phases,
Bert Marston
- How to generate 64-bit transfer?,
Taliaferro Smith
- help on PCI physical size,
Jennet Shi
- Where is standalone PCI arbiter chip?,
lecos
- 32 bit PCI, BAR -> FIFO.,
Xavi Neuri
- BIOS support for multiple host-PCI bridges on the same PCI bus,
neelay.das
- PCI slot lost on power up?,
Ivor Bowden
- Parallel Card,
Giovanni Brandi
- 32 bit PCI, Byte Lanes,
Xavi Neuri
- PCI Serial Card,
Marc Reviel
- Any suggestions?,
Elie Issa
- Fwd: RE: 32 bit / 3.3V PCI slots?,
Donald Connolly
- Query regarding Eq's of Master State Machine,
s-mallikarjuna.rao
- Membership for specific companies,
GYB2000
- Compaq PCI-X Verilog core,
Brent Barr
- pci design guide,
VENKATESHWARLU V" (by way of Daniel Weaver <dan.weaver@znyx.com>)
- Re: How to handle a requirement for dual PCI FPGA configuration serial bit streams.,
Eric Crabill (by way of Daniel Weaver <dan.weaver@znyx.com>)
- RE: PCI clock jitter,
Ingraham, Andrew
- How to handle a requirement for dual PCI FPGA configuration serial bitstreams.,
Jeffrey Journey
- Bridge throughput problems at 64bit/66Mhz,
Christer Olsson
- motherboards 654bit 66Mhz / and not with serverworks chipset,
Naert, Hans
- PCI-X 1.0 Specifications on Memory BARs,
Muthrasanallur, Sridhar
- Companies that sell PCI-X Test Environment,
Srividya Viswanathan
- PCI 64-bit master,
Tejendra Joshi
- PCI-IDE Bridge/Controller Chips,
John Weil
- host cycle,
Philex_Lin
- PMC BUSMODE[2..0],
Ivor Bowden
- Question on DAC,
James Murray
- Incorrect Target Termination?,
Konstantin Neskovic
- Motherbards with 64 bit/66 MHz PCI slots,
George Cosens
- SIG "approved" and OpenCores RE: New to forum!,
Lame Brooks-G14738 (by way of Daniel Weaver <dan.weaver@znyx.com>)
- New to forum!,
Miha Dolenc" (by way of Daniel Weaver <dan.weaver@znyx.com>)
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