PCI-X 2.0: High Performance, Backward Compatible PCI for the Future
Information about PCI-X 2.0
PCI-X 2.0 is a new, higher speed version of the conventional PCI standard, which supported signaling speeds up to 533 megatransfers per second (MTS). Revision 1.0 of the PCI-X specification defined PCI-X 66 and PCI-X 133 devices that transferred data up to 133 MTS, or over 1Gbyte per second for a 64-bit device. The present revision adds two new speed grades: PCI-X 266 and PCI-X 533, offering up to 4.3 gigabytes per second of bandwidth, 32 times faster than the first generation of PCI. Another major feature of the PCI-X 2.0 specification is enhanced system reliability. ECC support has been added both for the header and payload, providing automatic single-bit error recovery and double-bit error detection. These new standards keep pace with upcoming advances in high-bandwidth business-critical applications such as Fibre Channel, RAID, networking, InfiniBand™ Architecture, SCSI, and iSCSI.
PCI-X 2.0 is built upon the same architecture, protocols, signals, and connector as traditional PCI. The reuse of many of the design elements from the conventional PCI and PCI-X1.0b standards eases design and implementation migration. Migration to PCI-X 266 and PCI-X 533 is further simplified by retaining hardware and software compatibility with previous generations of PCI and PCI-X. As a result, new designs can immediately connect with hundreds of PCI and PCI-X products that are currently available. The combination of backwards compatibility and ease of migration provides investment protection for customers, developers, and manufacturers of existing PCI and PCI-X technologies as they migrate to PCI-X 266 and PCI-X 533.
PCI-X 2.0 also includes new features that will enhance applications in the future. It defines a new 16-bit interface width specifically designed for those applications that are constrained by space, such as embedded RAID controllers, or portable applications. PCI-X 2.0 also expands the device configuration space for each device-function to 4Kbytes, and defines a new Device ID Message transaction to enable simplified peer-to-peer transactions for applications such as streaming-media.
For over ten years, the PCI-SIG has been developing the world’s most popular bus technology. The PCI-X 2.0 266 MHz and 533 MHz standards lay the groundwork for the next decade, and further backwards-compatible extensions are planned beyond 533 MHz.
Summary of PCI-X 2.0 Features
PCI-X 2.0 Electrical Report:
Additional detailed supporting data referenced by the Electrical Report:
Other simulation tools (also available from sources outside the PCI-SIG):
PCI-X Marking Label:
About the PCI-X 2.0 Partners Page is a central resource for the PCI-X 2.0 community. Companies with products and services that support the development and launch of PCI-X 2.0 can make themselves known here.
PCI-X Review Zone contains the latest PCI-X material for member review. PCI-SIG Member benefits include the ability to influence the direction of PCI I/O Technology, review draft specifications, and participate in the ECR/ECN process. Be sure to check this page regularly for new material available for member review.
PCI-X 2.0 Technical Library contains links for more information on PCI-X 2.0, White Papers, and presentations from recent events, including the PCI-SIG Developers Conference.